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Caffe barista: brewing caffe with FPGAs in the training loop

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2006.13829v1.pdfWorking paper462.54 kBAdobe PDFView/Open
Title: Caffe barista: brewing caffe with FPGAs in the training loop
Authors: Vink, DA
Rajagopal, A
Venieris, SI
Bouganis, C-S
Item Type: Working Paper
Abstract: As the complexity of deep learning (DL) models increases, their compute requirements increase accordingly. Deploying a Convolutional Neural Network (CNN) involves two phases: training and inference. With the inference task typically taking place on resource-constrained devices, a lot of research has explored the field of low-power inference on custom hardware accelerators. On the other hand, training is both more compute- and memory-intensive and is primarily performed on power-hungry GPUs in large-scale data centres. CNN training on FPGAs is a nascent field of research. This is primarily due to the lack of tools to easily prototype and deploy various hardware and/or algorithmic techniques for power-efficient CNN training. This work presents Barista, an automated toolflow that provides seamless integration of FPGAs into the training of CNNs within the popular deep learning framework Caffe. To the best of our knowledge, this is the only tool that allows for such versatile and rapid deployment of hardware and algorithms for the FPGA-based training of CNNs, providing the necessary infrastructure for further research and development.
Issue Date: 18-Jun-2020
URI: http://hdl.handle.net/10044/1/80450
Publisher: arXiv
Copyright Statement: © 2020 The Author(s)
Sponsor/Funder: Huawei Technologies Co. Ltd
Funder's Grant Number: YBN2017070060
Keywords: cs.DC
cs.DC
cs.LG
cs.DC
cs.DC
cs.LG
Notes: Published as short paper at FPL2020
Publication Status: Published
Appears in Collections:Electrical and Electronic Engineering