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Yield modelling and yield enhancement for FPGAs using fault tolerance schemes
File | Description | Size | Format | |
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Yield modelling and yield.pdf | Published version | 261.02 kB | Adobe PDF | View/Open |
Title: | Yield modelling and yield enhancement for FPGAs using fault tolerance schemes |
Authors: | Campregher,N. Cheung,P.Y.K. Constantinides,G.A. Vasilko,M. |
Item Type: | Conference Paper |
Content Version: | Published version |
Issue Date: | 2005 |
URI: | http://hdl.handle.net/10044/1/1125 |
Publisher Link: | http://dx.doi.org/10.1109/FPL.2005.1515756 |
ISBN: | 0-7803-9362-7 9780780393622 |
Publisher: | IEEE |
Presented At: | International Conference on Field Programmable Logic and Applications, 24 - 26 August 2005 |
Start Page: | 409 |
End Page: | 414 |
Copyright Statement: | © 2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. |
Appears in Collections: | Circuits and Systems |