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Performance-area trade-off of address generators for address decoder- decoupled memory

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Title: Performance-area trade-off of address generators for address decoder- decoupled memory
Authors: Hettiaratchi,S.
Cheung,P.Y.K.
Clarke,T.J.W.
Item Type: Conference Paper
Content Version: Published version
Issue Date: 31-Dec-2002
URI: http://hdl.handle.net/10044/1/1073
Publisher Link: http://dx.doi.org/10.1109/DATE.2002.998407
ISBN: 0-7695-1472-3
9780769514727
Publisher: IEEE Computer Soc
Presented At: Design, Automation and Test in Europe Conference and Exhibition (2002), Paris, France, 4 - 8 March 2002
Start Page: 902
End Page: 908
Copyright Statement: © 2002 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.
Place of Publication: Los Alamitos
Appears in Collections:Circuits and Systems