Log-domain implementation of a processor for cochlear implant stimulators
File(s)
Author(s)
Belgaid, Yacine
Type
Thesis
Abstract
Globally, the number of people that live with disabling hearing loss as reported by the World Health Organisation is 430 million, with an additional 1 billion young adults at increased risk of hearing loss. In certain cases cochlear implants are prescribed, consisting of a visible, external processor which transmits signals across the skull to electrodes in the cochlea.
The aim of this thesis is to demonstrate that the contemporary digital signal processing (DSP) used in the processor can be replaced by log-domain, analogue circuits operating in the continuous-time, continuous-value domain. This work presents two such novel solutions. Firstly, a novel architecture that utilises an integrator core to estimate the Hilbert transform to extract the envelope and instantaneous frequency of signals. The design was simulated and then fabricated in 0.35 μm AMS technology and consumed 6.7 μW of power. Secondly, a novel memory-less n-of-m channel selector circuit implementation is proposed with O(n) complexity based on a hierarchical Winner Takes All (WTA) architecture. The implementation allows for a variable number of channels to be selected with each clock cycle by setting a single bias current. Channel selection number can be either of an integer value or based on the power spectral content contribution of the channels. The transistor-level design of a 16-channel selector was simulated and shown to support selection frequencies to at least 10 kHz. Combined with the filter-bank from previous research, the two blocks enable the implementation of all the speech coding strategies used in commercial cochlear implants, including fine-spectral processing (FSP). The thesis therefore demonstrated that it is feasible to implement cochlear implant processing in a single ultra-low power chip appropriate for a fully-implantable cochlear implant. Such a chip would be expected to provide high speech comprehension for cochlear implant users.
The aim of this thesis is to demonstrate that the contemporary digital signal processing (DSP) used in the processor can be replaced by log-domain, analogue circuits operating in the continuous-time, continuous-value domain. This work presents two such novel solutions. Firstly, a novel architecture that utilises an integrator core to estimate the Hilbert transform to extract the envelope and instantaneous frequency of signals. The design was simulated and then fabricated in 0.35 μm AMS technology and consumed 6.7 μW of power. Secondly, a novel memory-less n-of-m channel selector circuit implementation is proposed with O(n) complexity based on a hierarchical Winner Takes All (WTA) architecture. The implementation allows for a variable number of channels to be selected with each clock cycle by setting a single bias current. Channel selection number can be either of an integer value or based on the power spectral content contribution of the channels. The transistor-level design of a 16-channel selector was simulated and shown to support selection frequencies to at least 10 kHz. Combined with the filter-bank from previous research, the two blocks enable the implementation of all the speech coding strategies used in commercial cochlear implants, including fine-spectral processing (FSP). The thesis therefore demonstrated that it is feasible to implement cochlear implant processing in a single ultra-low power chip appropriate for a fully-implantable cochlear implant. Such a chip would be expected to provide high speech comprehension for cochlear implant users.
Version
Open Access
Date Issued
2022-06-11
Date Awarded
01/12/2023
Advisor
Drakakis, Emm Mic
Publisher Department
Bioengineering
Publisher Institution
Imperial College London
Qualification Level
Doctoral
Qualification Name
Doctor of Philosophy (PhD)