Pulse oximetry is widely used for brain tissue oxygenation measurement, where optical fibres crossing the patient's skull through a cranial bolt carry pulsed light from LEDs to the brain tissue while transferring the light reflected from the brain tissue to a current measuring photodiode. Pulse oximetry light detectors have evolved from a standalone, relatively small photodiode to an array of photodiodes that are spatially distributed around the pulsed LEDs. While novel photodiode arrays can provide a larger photocurrent by collecting a larger number of photons compared with the stand-alone version, and thereby provide better contrast, their relatively large output capacitance can significantly degrade the noise performance and the speed of the analogue front-end. This Thesis is dedicated to the design and fabrication of a novel front-end that can be used in conjunction with a modern photodiode to provide high-resolution brain tissue oxygenation measurement.

A novel low-power, ultra low noise pulse oximetry front-end is designed, fabricated, and tested in this study. This front-end encompasses a low noise novel transimpedance amplifier, which can handle modern photodiode arrays with large output capacitance. The front end is designed in a fashion that its input-referred RMS noise power always remains much weaker than that of the photodiode shot noise for all photocurrent DC levels within a range of interest, which, in turn, provides the maximum possible signal-to-noise ratio. The front-end also utilises a novel thermometric calibrator capable of adjusting the LED light intensity with respect to the photocurrent DC level. Therefore, if the signal DC level drops below a certain level, the LED light is increased to enhance the signal's strength; for signals with a high DC level, the LED light is decreased to save power. Finally, the front-end uses a correlated dual sampling technique to eliminate the dark current and offset errors.

In addition, this work analyses conventional pulse oximetry front-end topologies to specify the trade-offs and limitations posed by these architectures. All the theoretical and system level analyses are supported by transistor-level simulation data collected by means of Cadence Design Framework (CDF). These simulated results highlight the superiority of the proposed front-end design regarding power dissipation, silicon area usage, and noise performance in comparison with existing architectures.