LUTNet: Rethinking Inference in FPGA Soft Logic

Publication available at: http://arxiv.org/abs/1904.00938
Title: LUTNet: Rethinking Inference in FPGA Soft Logic
Authors: Wang, E
Davis, J
Cheung, P
Constantinides, G
Item Type: Conference Paper
Abstract: Research has shown that deep neural networks contain significant redundancy, and that high classification accuracies can be achieved even when weights and activations are quantised down to binary values. Network binarisation on FPGAs greatly increases area efficiency by replacing resource-hungry multipliers with lightweight XNOR gates. However, an FPGA's fundamental building block, the K-LUT, is capable of implementing far more than an XNOR: it can perform any K-input Boolean operation. Inspired by this observation, we propose LUTNet, an end-to-end hardware-software framework for the construction of area-efficient FPGA-based neural network accelerators using the native LUTs as inference operators. We demonstrate that the exploitation of LUT flexibility allows for far heavier pruning than possible in prior works, resulting in significant area savings while achieving comparable accuracy. Against the state-of-the-art binarised neural network implementation, we achieve twice the area efficiency for several standard network models when inferencing popular datasets. We also demonstrate that even greater energy efficiency improvements are obtainable.
Issue Date: 13-Jun-2019
Date of Acceptance: 3-Mar-2019
URI: http://hdl.handle.net/10044/1/68384
Publisher: IEEE
Copyright Statement: This paper is embargoed until publication.
Sponsor/Funder: Engineering & Physical Science Research Council (E
Royal Academy Of Engineering
Imagination Technologies Ltd
Commission of the European Communities
Engineering & Physical Science Research Council (EPSRC)
Funder's Grant Number: 11908 (EP/K034448/1)
Prof Constantinides Chair
Prof Constantinides Chair
671653
EP/P010040/1
Conference Name: IEEE Symposium on Field-programmable Custom Computing Machines (FCCM) 2019
Publication Status: Accepted
Start Date: 2019-04-28
Finish Date: 2019-05-01
Conference Place: San Diego, CA, USA
Embargo Date: publication subject to indefinite embargo
Open Access location: http://arxiv.org/abs/1904.00938
Appears in Collections:Electrical and Electronic Engineering



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