Polyhedral-based dynamic loop pipelining for high-level synthesis

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Title: Polyhedral-based dynamic loop pipelining for high-level synthesis
Authors: Liu, J
Wickerson, J
Bayliss, S
Constantinides, GA
Item Type: Journal Article
Abstract: Loop pipelining is one of the most important optimization methods in high-level synthesis (HLS) for increasing loop parallelism. There has been considerable work on improving loop pipelining, which mainly focuses on optimizing static operation scheduling and parallel memory accesses. Nonetheless, when loops contain complex memory dependencies, current techniques cannot generate high performance pipelines. In this paper, we extend the capability of loop pipelining in HLS to handle loops with uncertain dependencies (i.e., parameterized by an undetermined variable) and/or nonuniform dependencies (i.e., varying between loop iterations). Our optimization allows a pipeline to be statically scheduled without the aforementioned memory dependencies, but an associated controller will change the execution speed of loop iterations at runtime. This allows the augmented pipeline to process each loop iteration as fast as possible without violating memory dependencies. We use a parametric polyhedral analysis to generate the control logic for when to safely run all loop iterations in the pipeline and when to break the pipeline execution to resolve memory conflicts. Our techniques have been prototyped in an automated source-to-source code transformation framework, with Xilinx Vivado HLS, a leading HLS tool, as the RTL generation backend. Over a suite of benchmarks, experiments show that our optimization can implement optimized pipelines at almost the same clock speed as without our transformations, running approximately 3.7-10× faster, with a reasonable resource overhead.
Issue Date: 1-Sep-2018
Date of Acceptance: 4-Dec-2017
URI: http://hdl.handle.net/10044/1/54342
DOI: https://dx.doi.org/10.1109/TCAD.2017.2783363
Start Page: 1802
End Page: 1815
Journal / Book Title: IEEE Transactions on CAD of Integrated Circuits and Systems
Volume: 37
Copyright Statement: © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Sponsor/Funder: Engineering & Physical Science Research Council (EPSRC)
Engineering & Physical Science Research Council (E
Royal Academy Of Engineering
Imagination Technologies Ltd
Engineering & Physical Science Research Council (EPSRC)
Funder's Grant Number: EP/I020357/1
11908 (EP/K034448/1)
Prof Constantinides Chair
Prof Constantinides Chair
EP/P010040/1
Keywords: Science & Technology
Technology
Computer Science, Hardware & Architecture
Computer Science, Interdisciplinary Applications
Engineering, Electrical & Electronic
Computer Science
Engineering
Field-programmable gate array (FPGA)
high-level synthesis (HLS)
loop pipelining
polyhedral model
reconfigurable computing
0906 Electrical And Electronic Engineering
1006 Computer Hardware
Computer Hardware & Architecture
Publication Status: Published
Article Number: 9
Online Publication Date: 2017-12-14
Appears in Collections:Faculty of Engineering
Electrical and Electronic Engineering



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