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Results 1-10 of 16
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Issue DateTitleAuthor(s)
21-Feb-2016A Case for Work-Stealing on FPGAs with OpenCL AtomicsRamanathan, N; Wickerson, J; Winterstein, F; Constantinides, GA; , et al
1-Sep-2018Polyhedral-based dynamic loop pipelining for high-level synthesisLiu, J; Wickerson, J; Bayliss, S; Constantinides, GA; , et al
1-Jul-2018Scheduling weakly consistent C concurrency for reconfigurable hardwareRamanathan, N; Wickerson, J; Constantinides, GA; , et al
1-Jan-2017Automatically comparing memory consistency modelsWickerson, J; Batty, M; Sorensen, T; Constantinides, GA; , et al
10-Oct-2019Weak persistency semantics from the ground up: formalising the persistency semantics of ARMv8 and transactional modelsRaad, A; Wickerson, J; Vafeiadis, V;
20-Dec-2019Persistency semantics of the Intel-x86 architectureRaad, A; Wickerson, J; Neiger, G; Vafeiadis, V;
-Slow and steady: measuring and tuning multicore interferenceIorga, D; Sorensen, T; Wickerson, J; Donaldson, A;
13-Jan-2020Modulo scheduling with rational initiation intervals in custom hardware designSittel, P; Wickerson, J; Kumm, M; Zipf, P;
23-Feb-2020Finding and understanding bugs in FPGA synthesis toolsHerklotz Grave, Y; Wickerson, J;
-Combining dynamic and static scheduling in high-level synthesisCheng, J; Josipovic, L; Constantinides, G; Ienne, P; Wickerson, J, et al