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Issue DateTitleAuthor(s)
14-May-2018KOCL: Kernel-level power estimation for arbitrary FPGA-SoC-accelerated OpenCL applicationsDavis, JJ; Levine, J; Stott, E; Hung, E; Cheung, P, et al
25-Jun-2018Digit elision for arbitrary-accuracy iterative computationLi, H; Davis, JJ; Wickerson, J; Constantinides, G; Engineering & Physical Science Research Council (E, et al
27-Aug-2018Hardware compilation of deep neural networks: an overviewZhao, R; Liu, S; Ng, H; Wang, E; Davis, JJ, et al
9-Aug-2018An Application- and Platform-agnostic Control and Monitoring Framework for Multicore SystemsBragg, G; Leech, C; Balsamo, D; Wachter, E; Davis, JJ, et al
29-Apr-2018Concurrency-aware thread scheduling for high-level synthesisRamanathan, N; Constantinides, G; Wickerson, JP; Engineering & Physical Science Research Council (E; Imperial College London, et al
31-May-2019Deep neural network approximation for custom hardware: where we've been, where we're goingWang, E; Davis, J; Zhao, R; Ng, H; Niu, X, et al
13-Jun-2019LUTNet: Rethinking Inference in FPGA Soft LogicWang, E; Davis, J; Cheung, P; Constantinides, G; Engineering & Physical Science Research Council (E, et al
31-Jul-2018Automatic software and computing hardware co-design for predictive controlKhusainov, B; Kerrigan, EC; Constantinides, G; Commission of the European Communities; Engineering & Physical Science Research Council (E, et al