On-chip ID generation for multi-node implantable devices using SA-PUF

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Title: On-chip ID generation for multi-node implantable devices using SA-PUF
Author(s): Gao, C
Ghoreishizadeh, S
Liu, Y
Constandinou, TG
Item Type: Conference Paper
Abstract: This paper presents a 64-bit on-chip identification system featuring low power consumption and randomness compensation for multi-node bio-implantable devices. A sense amplifier based bit-cell is proposed to realize the silicon physical unclonable function, providing a unique value whose probability has a uniform distribution and minimized influence from the temperature and supply variation. The entire system is designed and implemented in a typical 0.35 m CMOS technology, including an array of 64 bit-cells, readout circuits, and digital controllers for data interfaces. Simulated results show that the proposed bit-cell design achieved a uniformity of 50.24% and a uniqueness of 50.03% for generated IDs. The system achieved an energy consumption of 6.0 pJ per bit with parallel outputs and 17.3 pJ per bit with serial outputs.
Publication Date: 28-May-2017
Date of Acceptance: 17-Feb-2017
URI: http://hdl.handle.net/10044/1/46110
Publisher: IEEE
Start Page: 678
End Page: 681
Copyright Statement: This paper is embargoed until publication
Sponsor/Funder: Wellcome Trust
Engineering & Physical Science Research Council (EPSRC)
Imperial College London
Funder's Grant Number: BH134389
EP/M020975/1
Conference Name: IEEE International Symposium on Circuits & Systems (ISCAS)
Publication Status: Accepted
Start Date: 2017-05-28
Finish Date: 2017-05-31
Conference Place: Baltimore, MD (USA)
Embargo Date: publication subject to indefinite embargo
Appears in Collections:Faculty of Engineering
Electrical and Electronic Engineering



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