A 4-wire interface SoC for shared multi-implant power transfer and full-duplex communication

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Title: A 4-wire interface SoC for shared multi-implant power transfer and full-duplex communication
Author(s): Ghoreishizadeh, S
Haci, D
Liu, Y
Constandinou, T
Item Type: Conference Paper
Abstract: This paper describes a novel system for recovering power and providing full-duplex communication over an AC- coupled 4-wire lead between active implantable devices. The target application requires a single Chest Device be connected to a Brain Implant consisting of multiple identical optrodes that record neural activity and provide closed loop optical stimulation. The interface is integrated within each optrode SoC allowing full-duplex and fully-differential communication based on Manchester encoding. The system features a head-to-chest uplink data rate (1.6 Mbps) that is higher than that of the chest- to-head downlink (100 kbps) superimposed on a power carrier. On-chip power management provides an unregulated 5 V DC supply with up to 2.5 mA output current for stimulation, and a regulated 3.3 V with 60 dB PSRR for recording and logic circuits. The circuit has been implemented in a 0.35 μ m CMOS technology, occupying 1.4 mm 2 silicon area, and requiring a 62.2 μ A average current consumption.
Publication Date: 20-Feb-2017
Date of Acceptance: 8-Dec-2016
URI: http://hdl.handle.net/10044/1/44160
Copyright Statement: This paper is embargoed until publication.
Conference Name: IEEE Latin American symposium on Circuits and Systems (LASCAS)
Publication Status: Accepted
Start Date: 2017-02-20
Finish Date: 2017-02-23
Conference Place: Bariloche, Argentina
Embargo Date: publication subject to indefinite embargo
Appears in Collections:Faculty of Engineering
Electrical and Electronic Engineering



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