An Unbiased MCMC FPGA-based Accelerator in the Land of Custom Precision Arithmetic

Title: An Unbiased MCMC FPGA-based Accelerator in the Land of Custom Precision Arithmetic
Author(s): Liu, S
Mingas, G
Bouganis, C
Item Type: Journal Article
Abstract: Markov Chain Monte Carlo (MCMC) based methods have been the main tool used for Bayesian Inference by practitioners and researchers due to their flexibility and theoretical properties that guarantee unbiased sampling-based estimates. Nevertheless, with the availability of large data sets and the constant need to develop more complex models that better capture the targeted problem, significant computational challenges have been presented. Current approaches, based on multi-core CPUs, GPUs, and FPGAs, aim to accelerate the execution time of the MCMC methods using subsampling techniques or custom precision arithmetic, resulting to biased estimates. In this work, a novel FPGA-based construction is proposed that utilises the custom precision support of FPGA devices in order to accelerate the computations, guaranteeing at the same time asymptotically unbiased estimates. Key to this approach is the extension of the parameter space by an extra parameter that indicates the required precision in the computation of the likelihood of a data point. The work proposes an FPGA architecture for the above algorithm, as well as discuss its tuning for maximising the performance of the system. The performance of the FPGA-mapped sampler is evaluated using two Bayesian logistic regression case studies of varying complexity, which show significant speedups compared to existing FPGA- and CPU-based works that utilise double floating point arithmetic, without any bias on the sampling-based estimates.
Publication Date: 18-Nov-2016
Date of Acceptance: 8-Nov-2016
URI: http://hdl.handle.net/10044/1/42491
DOI: https://dx.doi.org/10.1109/TC.2016.2630682
ISSN: 0018-9340
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Start Page: 745
End Page: 758
Journal / Book Title: IEEE Transactions on Computers
Volume: 66
Issue: 5
Copyright Statement: © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Sponsor/Funder: Engineering & Physical Science Research Council (EPSRC)
Wellcome Trust
Funder's Grant Number: EP/I012036/1
097816/Z/11/A
Keywords: Science & Technology
Technology
Computer Science, Hardware & Architecture
Engineering, Electrical & Electronic
Computer Science
Engineering
Field programmable gate array
Markov chain Monte Carlo
custom arithmetic precision
logistic regression
MNIST database
Computer Hardware & Architecture
0803 Computer Software
0805 Distributed Computing
1006 Computer Hardware
Publication Status: Published
Appears in Collections:Faculty of Engineering
Electrical and Electronic Engineering



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