Loop splitting for Efficient Pipelining in High-Level Synthesis

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Title: Loop splitting for Efficient Pipelining in High-Level Synthesis
Authors: Liu, J
Wickerson, J
Constantinides, GA
Item Type: Conference Paper
Abstract: Loop pipelining is widely adopted as a key optimization method in high-level synthesis (HLS). However, when complex memory dependencies appear in a loop, commercial HLS tools are still not able to maximize pipeline performance. In this paper, we leverage parametric polyhedral analysis to reason about memory dependence patterns that are uncertain (i.e., parameterised by an undetermined variable) and/or nonuniform (i.e., varying between loop iterations). We develop an automated source-to-source code transformation to split the loop into pieces, which are then synthesised by Vivado HLS as the hardware generation back-end. Our technique allows generated loops to run with a minimal interval, automatically inserting statically-determined parametric pipeline breaks at those iterations violating dependencies. Our experiments on seven representative benchmarks show that, compared to default loop pipelining, our parametric loop splitting improves pipeline performance by 4:3 in terms of clock cycles per iteration. The optimized pipelines consume 2:0 as many LUTs, 1:8 as many registers, and 1:1 as many DSP blocks. Hence the area-time product is improved by nearly a factor of 2.
Issue Date: 1-May-2016
Date of Acceptance: 1-Mar-2016
URI: http://hdl.handle.net/10044/1/32009
Publisher: IEEE
Copyright Statement: This article is under embargo until publication
Sponsor/Funder: Engineering & Physical Science Research Council (EPSRC)
Engineering & Physical Science Research Council (E
Royal Academy Of Engineering
Imagination Technologies Ltd
Funder's Grant Number: EP/I020357/1
11908 (EP/K034448/1)
Prof Constantinides Chair
Prof Constantinides Chair
Conference Name: IEEE International Symposium on Field-Programmable Custom Computing Machines
Publication Status: Accepted
Start Date: 2016-05-01
Finish Date: 2016-05-03
Conference Place: Washington, D.C., USA
Embargo Date: publication subject to indefinite embargo
Appears in Collections:Faculty of Engineering
Electrical and Electronic Engineering



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