Silicon nanowires for single slectron transistor fabrication

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Title: Silicon nanowires for single slectron transistor fabrication
Author(s): Wang, Chen
Item Type: Thesis or dissertation
Abstract: As the minimum feature sizes of current integrated circuits approach 10 nm, improvements in the speed, complexity and packing density are becoming increasingly difficult. In particular, at these scale, the operation of `classical' complementary metal-oxide-semiconductor (CMOS) devices is expected to degrade unacceptably. Single-electron devices, where the Coulomb blockade effect can be used to control charge at the one electron level, provide a means to fabricate large scale integration (LSI) circuits with ultra-low power consumption, immunity from charge fluctuations, and high scalability at sub-10 nm dimensions. Single-electron devices are potentially a successor technology to conventional classical Si metal-oxide-semiconductor field effect transistors (MOSFETs), and will play an increasingly important role both in future CMOS and `beyond CMOS' technologies. In this thesis, we first introduce the history of single-electron (SE) effects and the previous work in both theory and practical fabrication. Subsequently, the theoretical operation of the single-electron transistor (SET) is discussed, followed by a brief introduction to the quantum dot (QD) and the multiple tunnel junction (MTJ) transistor. The fabrication process for SET devices in heavily doped, n-type silicon-on-insulator (SOI) material, using the electron-beam lithography (EBL), is then introduced. Two types of Si SET devices have been studied, the 1 μm nanowire (NW) SET and `point gate' SET, which are both defined by EBL followed by reactive-ion etching (RIE) to create trench isolation of the devices, source, drain and nanowire regions. A thermal oxidation approach, was then used to reduce the Si core to the sub-10 nm scale in the NW. This passivates surface defects, creates charging 'islands' isolated by tunnel barriers and forms the SET. Variation in surface roughness, doping concentration and any disorder inherent at the nanoscale can form the tunnel barriers con ning the charging island. The SiNW SETs fabricated in this work have been electrically characterised at temperatures from 8 - 300 K. Results obtained from NWs with core widths from 5 nm to 40 nm with two di erent gate lengths of 1 μm to 50 nm have been compared. Here, detailed Ids vs. Vds, Vgs measurements have been performed at 8 K, and `Coulomb diamond' characteristics have been observed. The 1 μm long NWs behave as MTJs, with 40 nm scale islands. Here, the width of the Coulomb diamond cannot be reduced to zero. The detailed temperature dependence of the Ids vs. Vds characteristics show that some SE effects persist even at 300 K. The reduction in NW gate length to 50 nm reduces the likelihood of quantum dots to only three dots, but increases their influence on the electrical characteristics. In the point contact device, QD behaviour with a combination of SE charging and quantum confinement effects is observed at 8 K. In a highly scaled point circuit Coulomb blockade and a single-electron oscillation are observed. Monte Carlo simulations have been used to further investigate the devices and their island con gurations. The results of this thesis demonstrate explicitly the signicance of quantum effects for the electrical performance of nominally `classical' SiNW devices and highlight their potential for quantum effect `beyond CMOS' devices.
Content Version: Open Access
Publication Date: May-2015
Date Awarded: Oct-2015
Advisor: Durrani, Zahid
Department: Electrical and Electronic Engineering
Publisher: Imperial College London
Qualification Level: Doctoral
Qualification Name: Doctor of Philosophy (PhD)
Appears in Collections:Electrical and Electronic Engineering PhD theses

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