A scalable 32 channel neural recording and real-time FPGA based spike sorting system

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Title: A scalable 32 channel neural recording and real-time FPGA based spike sorting system
Authors: Williams, I
Luan, S
Jackson, A
Constandinou, TG
Item Type: Conference Paper
Abstract: This demo presents a scalable a 32-channel neural recording platform with real-time, on-node spike sorting ca- pability. The hardware consists of: an Intan RHD2132 neural amplifier; a low power Igloo ® nano FPGA; and an FX3 USB 3.0 controller. Graphical User Interfaces for controlling the system, displaying real-time data, and template generation with a modified form of WaveClus are demonstrated.
Issue Date: 24-Oct-2015
Date of Acceptance: 10-Aug-2015
URI: http://hdl.handle.net/10044/1/27018
DOI: https://dx.doi.org/10.1109/BioCAS.2015.7348330
Publisher: IEEE
Start Page: 187
End Page: 191
Copyright Statement: © 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Sponsor/Funder: Engineering & Physical Science Research Council (EPSRC)
Engineering & Physical Science Research Council (EPSRC)
Engineering & Physical Science Research Council (EPSRC)
Engineering & Physical Science Research Council (EPSRC)
Engineering & Physical Science Research Council (E
Funder's Grant Number: EP/I000569/1
EP/I000569/1
EP/K015060/1
EP/M020975/1
BH141353 (EP/M025977/1)
Conference Name: IEEE Biomedical Circuits and Systems (BioCAS) Conference
Publication Status: Published
Start Date: 2015-10-22
Finish Date: 2015-10-24
Conference Place: Atlanta, GA
Appears in Collections:Faculty of Engineering
Electrical and Electronic Engineering



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