Delay-Bounded Routing for Shadow Registers

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Title: Delay-Bounded Routing for Shadow Registers
Authors: Hung, E
Levine, J
Stott, E
Constantinides, G
Luk, W
Item Type: Conference Paper
Abstract: The on-chip timing behaviour of synchronous circuits can be quantified at run-time by adding shadow registers, which allow designers to sample the most critical paths of a circuit at a different point in time than the user register would normally. In order to sample these paths precisely, the path skew between the user and the shadow register must be tightly controlled and consistent across all paths that are shadowed. Unlike a custom IC, FPGAs contain prefabricated resources from which composing an arbitrary routing delay is not trivial. This paper presents a method for inserting shadow registers with a minimum skew bound, whilst also reducing the maximum skew. To preserve circuit timing, we apply this to FPGA circuits post place-and-route, using only the spare resources left behind. We find that our techniques can achieve an average STA reported delay bound of ±200ps on a Xilinx device despite incomplete timing information, and achieve <1ps accuracy against our own delay model.
Issue Date: 22-Feb-2015
ISBN: 978-1-4503-3315-3
Publisher: Association for Computing Machinery.
Start Page: 56
End Page: 65
Journal / Book Title: FPGA '15 Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
Copyright Statement: © ACM, 2015. This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version was published in FPGA '15 Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015.
Conference Name: 23rd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
Conference Place: Monterey, Ca
Appears in Collections:Computing
Electrical and Electronic Engineering

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