Yield modelling and yield enhancement for FPGAs using fault tolerance schemes

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Title: Yield modelling and yield enhancement for FPGAs using fault tolerance schemes
Author(s): Campregher,N.
Item Type: Conference Paper
Content Version: Published version
Publication Date: 2005
URI: http://hdl.handle.net/10044/1/1125
Publisher Link: http://dx.doi.org/10.1109/FPL.2005.1515756
ISBN: 0-7803-9362-7
Publisher: IEEE
Presented At: International Conference on Field Programmable Logic and Applications, 24 - 26 August 2005
Start Page: 409
End Page: 414
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Appears in Collections:Circuits and Systems

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