Zhou, HHZhouNiu, XXNiuYuan, JJYuanWang, LLWangLuk, WWLuk2016-07-042016-09-292016http://hdl.handle.net/10044/1/34335This paper introduces cycle-reconfigurable modules that enhance FPGA architectures with efficient support for dynamic data accesses: data accesses with accessed data size and location known only at runtime. The proposed module adopts new reconfiguration strategies based on dynamic FIFOs , dynamic caches , and dynamic shared memories to significantly reduce configuration generation and routing complexity. We develop a prototype FPGA chip with the proposed cycle-reconfigurable module in the SMIC 130-nm technology. The integrated module takes less than the chip area of 39 CLBs, and reconfigures thousands of runtime connections in 1.2 ns. Applications for large- scale sorting, sparse matrix-vector multiplication, and Mem- cached are developed. The proposed modules enable 1.4 and 11 times reductions in area-delay product compared with those applications mapped to previous architectures and conventional FPGAs.© 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Science & TechnologyTechnologyComputer Science, Software EngineeringEngineering, Electrical & ElectronicComputer ScienceEngineeringConference Paperhttps://www.dx.doi.org/10.1109/FPL.2016.7577332https://ieeexplore.ieee.org/document/757733220104124671653EP/K503733/1EP/I012036/1EP/K011715/1