High-level synthesis using the Julia language

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Title: High-level synthesis using the Julia language
Authors: Biggs, B
McInerney, I
Kerrigan, EC
Constantinides, GA
Item Type: Conference Paper
Abstract: The growing proliferation of FPGAs and High-level Synthesis (HLS) tools has led to a large interest in designing hardware accelerators for complex operations and algorithms. However, existing HLS toolflows typically require a significant amount of user knowledge or training to be effective in both industrial and research applications. In this paper, we propose using the Julia language as the basis for an HLS tool. The Julia HLS tool aims to decrease the barrier to entry for hardware acceleration by taking advantage of the readability of the Julia language and by allowing the use of the existing large library of standard mathematical functions written in Julia. We present a prototype Julia HLS tool, written in Julia, that transforms Julia code to VHDL. We highlight how features of Julia and its compiler simplified the creation of this tool, and we discuss potential directions for future work.
Date of Acceptance: 9-Feb-2022
URI: http://hdl.handle.net/10044/1/95997
Copyright Statement: © 2022 Copyright held by the owner/author(s)
Conference Name: 2nd Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE’22)
Keywords: cs.SE
Publication Status: Published
Start Date: 2022-03-01
Conference Place: Lausanne, Switzerland
Appears in Collections:Electrical and Electronic Engineering