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Reconfigurable acceleration of big data analytics
File | Description | Size | Format | |
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Philippos-P-2021-PhD-Thesis.pdf | Thesis | 3.62 MB | Adobe PDF | View/Open |
Title: | Reconfigurable acceleration of big data analytics |
Authors: | Papaphilippou, Philippos |
Item Type: | Thesis or dissertation |
Abstract: | The amount of data stored and processed in data centers is growing at an unprecedented rate. At the same time, the improvement in processing capabilities of central processing units (CPUs) has relatively stagnated over the last decade, creating an increasing demand for specialised processing. Specialised accelerators have gotten the spotlight for computationally intensive applications, such as with deep learning on graphics processing units (GPUs), though such special purpose processors tend to be optimised for the trending applications and are not efficient for each entity’s computational needs. On the other hand, reconfigurable computing has shown impressive potential in accelerating specialised tasks, including database applications. Hence, field-programmable gate arrays (FPGAs) have started evolving into an integral part in the data center. However, the heterogeneity found in today’s systems featuring FPGAs, such as through non-uniform memory accesses (NUMA), has complicated the deployment and development of database accelerators. This PhD introduces novel parallel algorithms and FPGA designs for database acceleration that take into consideration the inter-chip communication limitations. The presented designs accelerate fundamental database operators such as sorting, sort-merge join and distinct count, with notable advantages over the state-of-the-art. Additionally, some building blocks such as the parallel round-robin arbiter and the fast lightweight merge sorter (FLiMS) are shown to have a wider applicability, including in single-instruction multiple-data (SIMD) algorithms and network switches. The proposed designs operate in a streaming access pattern with a wide path in order to achieve scalability to input size and future high-bandwidth architectures. Finally, a discussion on future architectures with reconfigurable instructions is provided as future work to further address the challenges appearing when accelerating big data using today’s FPGAs. |
Content Version: | Open Access |
Issue Date: | May-2021 |
Date Awarded: | Oct-2021 |
URI: | http://hdl.handle.net/10044/1/94446 |
DOI: | https://doi.org/10.25560/94446 |
Copyright Statement: | Creative Commons Attribution NonCommercial Licence |
Supervisor: | Luk, Wayne |
Sponsor/Funder: | dunnhumby (Firm) Engineering and Physical Sciences Research Council |
Funder's Grant Number: | PO: 250130012887 |
Department: | Computing |
Publisher: | Imperial College London |
Qualification Level: | Doctoral |
Qualification Name: | Doctor of Philosophy (PhD) |
Appears in Collections: | Computing PhD theses |
This item is licensed under a Creative Commons License