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Microsystem integration and packaging for chip-scale implantable devices

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Szostak-Lipowicz-K-2021-PhD-Thesis.pdf86.55 MBAdobe PDFView/Open
Title: Microsystem integration and packaging for chip-scale implantable devices
Authors: Szostak-Lipowicz, Katarzyna
Item Type: Thesis or dissertation
Abstract: As a consequence of the progress in miniaturisation technology and material science in the late 20th century, there has been a remarkable development in the form factors and technologies applied to biomedical microsystems, such as implantable neural interfaces. Over time implants dimensions have significantly shrunk while simultaneously their complexity such as the ability to connect to more electrodes, increased. Notwithstanding these efforts, the promise of fully implantable brain-machine interfacing systems capable of wireless performance over large cortical areas is yet to be accomplished. Challenges in system integration, implant fabrication and packaging are recognised as the key aspects requiring further advancements on the road towards the future of clinical neural interfaces. Particularly for systems composed of multiple distributed implants, where the relation between their number and size is inversely proportional, it is of utmost significance to reduce the packaging size to the minimum while effectively protecting both the device from deterioration and the host tissue from inflammation. In addition to environmental protection, an implant’s package must provide reliable interconnections between the interfacing electrodes and electronic modules responsible for data conditioning and processing. As a consequence, the design of autonomous miniaturised neural interfaces faces a set of challenges that need to be addressed to assure a stable long-term performance. These include implant’s compatibility with the biological environment, the safety of its Complementary Metal Oxide Semiconductor (CMOS) electronics and wireless communication, as well as a selection of a fabrication process adaptable to mass manufacturing. The underlying aim of this research is thus to investigate the feasibility of CMOS-compatible packaging and integration scheme for distributed mm-scale neural implants, design of a biocompatible hermetic sealing method applicable for chronic applications, and demonstration of a non-toxic approach to achieve repeatable gold-tin alloys for implementation in sensors packaging. The original contributions of this work are summarised as three aspects. Contribution 1 - The development of the structural design, along with the fabrication method and the proof of concept realisation of two versions of mm-sized autonomous neural implant based on microwire electrodes. The design considers the need for the device’s compatibility with the biological environment, CMOS electronics and RF communication. Initial mechanical structures are fabricated and described in detail, along with the presentation of a method for a microwire integration. Contribution 2 - The development of a repeatable, CMOS-compatible method of hermetic packaging for use in implantable devices. The proposed technique employs silicon to silicon eutectic bonding through gold-tin layers resulting in the average bonding strength of 28 MPa with a bonding yield of 73%. Identification of the preferred geometry aspects from the mechanical stability and reliability perspectives was made by the series of shear force tests, scanning electron microscopy and scanning acoustic microscopy inspections, and immersion tests. Contribution 3 - A method for repeatable, low-hazard, low-volume sequential electrochemical deposition of gold-tin alloys of controllable composition on silicon substrates is developed and optimised to achieve the minimum possible roughness with the best repeatability of deposited layers thickness. This was done by analysing the influence of several electroplating parameters on the grain morphology and deposit thickness deviations across substrates. The proposed technique is based on commercially available chemistry and does not require strict bath maintenance. This work proposes the structural design and packaging methods utilisable in the realisation of millimetre-sized, microwire-based implantable neural interfaces, with an emphasis on the importance of package structural integrity, biocompatibility and manufacturability. I envisage that with further improvements, the proposed approach could be employed in the large scale fabrication of distributed implantable neural interfacing devices.
Content Version: Open Access
Issue Date: Aug-2021
Date Awarded: Dec-2021
URI: http://hdl.handle.net/10044/1/93817
DOI: https://doi.org/10.25560/93817
Copyright Statement: Creative Commons Attribution NonCommercial NoDerivatives Licence
Supervisor: Constandinou, Timothy
Sponsor/Funder: Engineering and Physical Sciences Research Council
Funder's Grant Number: EP/M020975/1
Department: Electrical and Electronic Engineering
Publisher: Imperial College London
Qualification Level: Doctoral
Qualification Name: Doctor of Philosophy (PhD)
Appears in Collections:Electrical and Electronic Engineering PhD theses



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