Enhancing FPGA applications by applying codecs to data channels

Abstract

FPGA streaming systems are well suited for high-performance computing (HPC) applications, where the parallelism of algorithms can be exploited using pipelines. The usage of FPGAs have become more common with increasing computational demand, since FPGAs have been very effective at meeting the demand.

Streaming systems are often implemented on heterogeneous platforms, where hardware accelerators on FPGAs are coupled with CPUs. In such cases, the programmer can achieve an improvement in performance by performing the computationally intensive parts of an algorithm on the FPGA. This way, the relative advantages of both software and hardware computation can be exploited. There are, however, challenges that heterogeneous systems face, which are limiting the performance that can be achieved.

This report explores a framework to enhance properties of data channels which transmit data to/from an FPGA kernel. Currently, the framework is applied to a PCI-express channel between an FPGA kernel and a CPU on a heterogeneous CPU-FPGA system by using of spare CPU and FPGA resources. Compute-intensive codecs such as compression are applied at line rate while maintaining the simplicity of a high-level abstraction. Encoding/decoding is done by splitting the data stream into segments and having multiple codec threads processing different segments. Multi-threading in software also allows the overlap of encoding, data transmission and decoding thereby functioning as a software pipeline. Hardware codecs are pipelined.

A number of compression codecs are applied using the framework and a model is developed to predict the run-time performance when codecs are applied, without the need to do a full implementation and benchmark.