Fast turnaround fabrication of silicon point-contact quantum-dot transistors using combined thermal scanning probe lithography and laser writing.

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Title: Fast turnaround fabrication of silicon point-contact quantum-dot transistors using combined thermal scanning probe lithography and laser writing.
Authors: Rawlings, CD
Ryu, YK
Rüegg, M
Lassaline, N
Schwemmer, C
Duerig, U
Knoll, A
Durrani, ZAK
Wang, C
Liu, D
Jones, ME
Item Type: Journal Article
Abstract: The fabrication of high-performance solid-state silicon quantum-devices requires high resolution patterning with minimal substrate damage. We have fabricated room temperature single-electron transistors (SETs) based on point-contact tunnel junctions using a hybrid lithography tool capable of both high resolution thermal scanning probe lithography and high throughput direct laser writing. The best focal z-position and the offset of the tip- and the laser-writing positions were determined in-situ with the scanning probe. We demonstrate < 100 nm precision in the registration between the high resolution and high throughput lithographies. The SET devices were fabricated on degenerately doped n-type > 1020/cm3 silicon on insulator (SOI) chips using a CMOS compatible geometric oxidation process. The characteristics of the three devices investigated were dominated by the presence of Si nanocrystals or phosphorous atoms embedded within the SiO2, forming quantum dots (QDs). The small size and strong localisation of electrons on the QDs facilitated SET operation even at room temperature. Temperature measurements showed that in the range 300 K > T > ~100 K, the current flow was thermally activated but at < 100 K, it was dominated by tunnelling.
Issue Date: 12-Oct-2018
Date of Acceptance: 24-Sep-2018
URI: http://hdl.handle.net/10044/1/63394
DOI: https://dx.doi.org/10.1088/1361-6528/aae3df
ISSN: 0957-4484
Publisher: IOP Publishing
Journal / Book Title: Nanotechnology
Volume: 29
Issue: 50
Copyright Statement: © 2018 IOP Publishing Ltd. This is an author-created, un-copyedited version of an article accepted for publication in Nanotechnology. IOP Publishing Ltd is not responsible for any errors or omissions in this version of the manuscript or any version derived from it. The definitive publisher authenticated version is available online at https://dx.doi.org/10.1088/1361-6528/aae3df
Sponsor/Funder: Commission of the European Communities
Funder's Grant Number: 318804
Keywords: laser writing
mix and match processing
nanofabrication
single electron transistor
thermal scanning probe lithography
MD Multidisciplinary
Nanoscience & Nanotechnology
Publication Status: Published
Conference Place: England
Embargo Date: 2019-10-12
Online Publication Date: 2018-09-24
Appears in Collections:Faculty of Engineering
Electrical and Electronic Engineering



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