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Hardware compilation of deep neural networks: an overview

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Title: Hardware compilation of deep neural networks: an overview
Authors: Zhao, R
Liu, S
Ng, H
Wang, E
Davis, JJ
Niu, X
Wang, X
Shi, H
Constantinides, G
Cheung, P
Luk, W
Item Type: Conference Paper
Abstract: Deploying a deep neural network model on a reconfigurable platform, such as an FPGA, is challenging due to the enormous design spaces of both network models and hardware design. A neural network model has various layer types, connection patterns and data representations, and the corresponding implementation can be customised with different architectural and modular parameters. Rather than manually exploring this design space, it is more effective to automate optimisation throughout an end-to-end compilation process. This paper provides an overview of recent literature proposing novel approaches to achieve this aim. We organise materials to mirror a typical compilation flow: front end, platform-independent optimisation and back end. Design templates for neural network accelerators are studied with a specific focus on their derivation methodologies. We also review previous work on network compilation and optimisation for other hardware platforms to gain inspiration regarding FPGA implementation. Finally, we propose some future directions for related research.
Issue Date: 27-Aug-2018
Date of Acceptance: 23-Jun-2018
URI: http://hdl.handle.net/10044/1/62208
DOI: https://dx.doi.org/10.1109/ASAP.2018.8445088
ISSN: 2160-052X
Publisher: IEEE
Journal / Book Title: 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP)
Copyright Statement: © 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Sponsor/Funder: Engineering & Physical Science Research Council (EPSRC)
Engineering & Physical Science Research Council (E
Commission of the European Communities
Engineering & Physical Science Research Council (E
Funder's Grant Number: EP/I012036/1
11908 (EP/K034448/1)
516075101 (EP/N031768/1)
Conference Name: IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2018
Publication Status: Published
Start Date: 2018-07-10
Finish Date: 2018-07-12
Conference Place: Milan, Italy
Appears in Collections:Faculty of Engineering
Electrical and Electronic Engineering

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