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f-CNNx: a toolflow for mapping multiple convolutional neural networks on FPGAs

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Title: f-CNNx: a toolflow for mapping multiple convolutional neural networks on FPGAs
Authors: Venieris, SI
Bouganis, C-S
Item Type: Conference Paper
Abstract: The predictive power of Convolutional Neural Networks (CNNs) has been an integral factor for emerging latency-sensitive applications, such as autonomous drones and vehicles. Such systems employ multiple CNNs, each one trained for a particular task. The efficient mapping of multiple CNNs on a single FPGA device is a challenging task as the allocation of compute resources and external memory bandwidth needs to be optimised at design time. This paper proposes f-CNNx, an automated toolflow for the optimised mapping of multiple CNNs on FPGAs, comprising a novel multi-CNN hardware architecture together with an automated design space exploration method that considers the user-specified performance requirements for each model to allocate compute resources and generate a synthesisable accelerator. Moreover, f-CNNx employs a novel scheduling algorithm that alleviates the limitations of the memory bandwidth contention between CNNs and sustains the high utilisation of the architecture. Experimental evaluation shows that f-CNNx's designs outperform contention-unaware FPGA mappings by up to 50% and deliver up to 6.8x higher performance-per-Watt over highly optimised GPU designs for multi-CNN systems.
Date of Acceptance: 25-May-2018
URI: http://hdl.handle.net/10044/1/60780
Conference Name: 28th International Conference on Field Programmable Logic and Applications
Keywords: Science & Technology
Technology
Computer Science, Hardware & Architecture
Computer Science, Software Engineering
Computer Science
cs.CV
cs.CV
cs.AI
cs.AR
Publication Status: Unpublished
Start Date: 2018-08-27
Finish Date: 2018-08-31
Conference Place: Trinity College, Dublin, Republic of Ireland
Appears in Collections:Electrical and Electronic Engineering
Faculty of Engineering



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