Co-design of FPGA implementations for model predictive control

Abstract

Model Predictive Control (MPC) is an advanced control method that is capable of explicit performance optimization, systematic constraint handling and dealing with nonlinearities in a natural way. The necessity of solving an optimization problem at each sampling instant makes MPC a computationally demanding technique, especially when applied to fast dynamical systems. This thesis is concerned with developing efficient hardware implementations of linear and nonlinear model predictive controllers.

In the first part of this thesis, a software toolchain for quick prototyping of embedded optimization algorithms on Field-Programmable Gate Arrays (FPGAs) is presented. The toolchain consists of two software tools: SPLIT and Protoip. SPLIT is capable of generating CPU and FPGA-oriented C code for embedded optimization using operator splitting methods. The generated code can be automatically deployed and tested on an embedded platform using a new release of Protoip, a software tool for quick prototyping of optimization algorithm on CPUs, FPGAs and heterogeneous platforms that incorporate both general-purpose processors and reconfigurable logic.

The second part presents a framework for implementation of nonlinear model predictive control on a heterogeneous computing platform. Splitting the computational workload between a general-purpose CPU and an FPGA allows exploiting the strengths of each computational subsystem and trading off control performance against reconfigurable logic usage. A new method for scheduling sparse matrix-vector multiplication within the proposed implementation enables significant improvements in terms of memory and computational resources usage.

The third part of this thesis presents an application of systematic optimization to the co-design of MPC software and computational hardware. A procedure for formulating the MPC design problem as a multi-objective optimization problem is described. Finally, two test cases including CPU and FPGA-based implementations of predictive controllers are considered.