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A 64-Channel Versatile Neural Recording SoC with Activity Dependant Data Throughput

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Title: A 64-Channel Versatile Neural Recording SoC with Activity Dependant Data Throughput
Authors: Liu, Y
Luan, S
Williams, I
Rapeaux, A
Constandinou, TG
Item Type: Journal Article
Abstract: Modern microtechnology is enabling the channel count of neural recording integrated circuits to scale exponentially. However, the raw data bandwidth of these systems is increasing proportionately, presenting major challenges in terms of power consumption and data transmission (especially for wireless systems). This paper presents a system that exploits the sparse nature of neural signals to address these challenges and provides a reconfigurable low-bandwidth event-driven output. Specifically, we present a novel 64-channel low noise (2.1μVrms, low power (23μW per analogue channel) neural recording system-on-chip (SoC). This features individually-configurable channels, 10-bit analogue-to-digital conversion, digital filtering, spike detection, and an event-driven output. Each channel's gain, bandwidth & sampling rate settings can be independently configured to extract Local Field Potentials (LFPs) at a low data-rate and/or Action Potentials (APs) at a higher data rate. The sampled data is streamed through an SRAM buffer that supports additional on-chip processing such as digital filtering and spike detection. Real-time spike detection can achieve ~2 orders of magnitude data reduction, by using a dual polarity simple threshold to enable an event driven output for neural spikes (16-sample window). The SoC additionally features a latency-encoded asynchronous output that is critical if used as part of a closed-loop system. This has been specifically developed to complement a separate on-node spike sorting co-processor to provide a real-time (low latency) output. The system has been implemented in a commercially-available 0.35μm CMOS technology occupying a silicon area of 19.1mm² (0.3mm² gross per channel), demonstrating a low power & efficient architecture which could be further optimised by aggressive technology and supply voltage scaling.
Issue Date: 31-Dec-2017
Date of Acceptance: 25-Sep-2017
URI: http://hdl.handle.net/10044/1/51243
DOI: https://dx.doi.org/10.1109/TBCAS.2017.2759339
ISSN: 1932-4545
Publisher: Institute of Electrical and Electronics Engineers
Start Page: 1344
End Page: 1355
Journal / Book Title: IEEE Transactions on Biomedical Circuits and Systems
Volume: 11
Issue: 6
Copyright Statement: This is an open access article freely available at https://dx.doi.org/10.1109/TBCAS.2017.2759339
Sponsor/Funder: Engineering & Physical Science Research Council (EPSRC)
Engineering & Physical Science Research Council (EPSRC)
Wellcome Trust
Engineering & Physical Science Research Council (EPSRC)
Funder's Grant Number: EP/I000569/1
EP/K015060/1
BH134389
EP/M020975/1
Keywords: 0903 Biomedical Engineering
0906 Electrical And Electronic Engineering
Electrical & Electronic Engineering
Publication Status: Published online
Appears in Collections:Faculty of Engineering
Electrical and Electronic Engineering



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