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Results 1-10 of 30
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Issue DateTitleAuthor(s)
13-Jul-2015Certified Roundoff Error Bounds Using Semidefinite Programming.Magron, V; Constantinides, GA; Donaldson, AF; Engineering & Physical Science Research Council (EPSRC); Engineering & Physical Science Research Council (EPSRC), et al
18-Aug-2016KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA DesignsHung, E; Davis, JJ; Levine, JM; Stott, EA; Cheung, PYK, et al
4-Sep-2017STRIPE: signal selection for runtime power estimationDavis, J; Levine, J; Stott, E; Hung, E; Cheung, P, et al
21-Feb-2016Knowledge is Power: Module-level Sensing for Runtime OptimisationDavis, JJ; Hung, E; Levine, J; Stott, E; Cheung, PYK, et al
22-Feb-2017Hardware synthesis of weakly consistent C concurrencyRamanathan, N; Fleming, S; Wickerson, J; Constantinides, GA; Engineering & Physical Science Research Council (EPSRC), et al
11-Sep-2017KOCL: Power Self-awareness for Arbitrary FPGA-SoC-accelerated OpenCL ApplicationsDavis, JJ; Levine, JM; Stott, EA; Hung, E; Cheung, PYK, et al
8-Jul-2013Controlling the neuronal balancing act: optical coactivation of excitation and inhibition in neuronal subdomainsNikolic, K; Jarvis, S; Schultz, S; Grossman, N; The Royal Society, et al
21-Feb-2016A Case for Work-Stealing on FPGAs with OpenCL AtomicsRamanathan, N; Wickerson, J; Winterstein, F; Constantinides, GA; Engineering & Physical Science Research Council (EPSRC), et al
1-May-2016Loop splitting for Efficient Pipelining in High-Level SynthesisLiu, J; Wickerson, J; Constantinides, GA; Engineering & Physical Science Research Council (EPSRC); Engineering & Physical Science Research Council (E, et al
1-Sep-2018Polyhedral-based dynamic loop pipelining for high-level synthesisLiu, J; Wickerson, J; Bayliss, S; Constantinides, GA; Engineering & Physical Science Research Council (EPSRC), et al