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Results 1-10 of 30
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Issue DateTitleAuthor(s)
13-Jul-2015Certified Roundoff Error Bounds Using Semidefinite Programming.Magron, V; Constantinides, GA; Donaldson, AF; Engineering & Physical Science Research Council (EPSRC); Engineering & Physical Science Research Council (EPSRC), et al
18-Aug-2016KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA DesignsHung, E; Davis, JJ; Levine, JM; Stott, EA; Cheung, PYK, et al
4-Sep-2017STRIPE: signal selection for runtime power estimationDavis, J; Levine, J; Stott, E; Hung, E; Cheung, P, et al
20-Nov-2013Constrained LQR for low-precision data representationLongo, S; Kerrigan, EC; Constantinides, GA; Engineering & Physical Science Research Council (E; Engineering & Physical Science Research Council (E
18-Jul-2013Predictive control using an FPGA with application to aircraft controlHartley, EN; Jerez, JL; Suardi, A; Maciejowski, JM; Kerrigan, EC, et al
21-Feb-2016Knowledge is Power: Module-level Sensing for Runtime OptimisationDavis, JJ; Hung, E; Levine, J; Stott, E; Cheung, PYK, et al
22-Feb-2017Hardware synthesis of weakly consistent C concurrencyRamanathan, N; Fleming, S; Wickerson, J; Constantinides, GA; Engineering & Physical Science Research Council (EPSRC), et al
11-Sep-2017KOCL: Power Self-awareness for Arbitrary FPGA-SoC-accelerated OpenCL ApplicationsDavis, JJ; Levine, JM; Stott, EA; Hung, E; Cheung, PYK, et al
9-Jan-2018KAPow: high-accuracy, low-overhead online per-module power estimation for FPGA designsDavis, JJ; Hung, E; Levine, JM; Stott, EA; Cheung, PYK, et al
1-Aug-2012Model predictive control for deeply pipelined field-programmable gate array implementation: algorithms and circuitryJerez, JL; Ling, KV; Constantinides, GA; Kerrigan, EC; Engineering & Physical Science Research Council (E