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Brain machine interfaces: low power techniques for CMOS based system integration

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Title: Brain machine interfaces: low power techniques for CMOS based system integration
Authors: Leene, Lieuwe
Item Type: Thesis or dissertation
Abstract: The emergence of miniaturized electronic sensors for recording neural activity is opening up new opportunities for better health care and understanding brain function. The precise instrumentation for sensing these signals has been developed extensively, but no implantable system available today is capable of providing a high density recording structures that can be scaled to accommodate the large number of electrodes and processing neuroprosthetics need for functional limb replacement. The design of these systems is complicated by micro-volt levels of signal that contain convoluted mixtures of information. This demands highly accurate signal quantization and exhaustive processing that is constrained by the scarce power availability. The resulting difficulty in realizing viable solutions for chronic implants necessitates cutting-edge fabrication technologies and state-of-the-art circuit optimization techniques. This thesis presents the understanding behind optimizing these instrumentation systems in order to maximize the simultaneous sensing capabilities of brain machine interfaces that can be implanted wirelessly into living systems. These analytics enabled this work to outperform state of the art in terms of delivering high precision at 56 dB SINAD with a sub 0.01mm^2 silicon footprint and a 800 nW power budget by employing novel time-domain circuit techniques. This advancement will enable BMIs to be integrated & minimutrized using nanometre CMOS with extensive digital processing capabilities that are capable of decoding neural signals without supervision such that therapy in a fully implanted fashion. Moreover by introducing distributed processing architecture this work is the first to allows scalable fully reconfigurable functionality at the instrumentation interface for complex algorithmic operations while maintaining a power efficiency of 2.7μW per MIPS.
Content Version: Open Access
Issue Date: May-2016
Date Awarded: Dec-2016
URI: http://hdl.handle.net/10044/1/47980
DOI: https://doi.org/10.25560/47980
Supervisor: Constandinou, Timothy
Department: Electrical and Electronic Engineering
Publisher: Imperial College London
Qualification Level: Doctoral
Qualification Name: Doctor of Philosophy (PhD)
Appears in Collections:Electrical and Electronic Engineering PhD theses

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