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A nanosecond-level hybrid table design for financial market data generators
File | Description | Size | Format | |
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fccm17ch.pdf | Accepted version | 339.4 kB | Adobe PDF | View/Open |
Title: | A nanosecond-level hybrid table design for financial market data generators |
Authors: | Fu, H He, C Luk, W Li, W Yang, G |
Item Type: | Conference Paper |
Abstract: | This paper proposes a hybrid sorted table design for minimizing electronic trading latency, with three main contributions. First, a hierarchical sorted table with two levels, a fast cache table in reconfigurable hardware storing megabytes of data items and a master table in software storing gigabytes of data items. Second, a full set of operations, including insertion, deletion, selection and sorting, for the hybrid table with latency in a few cycles. Third, an on- demand synchronization scheme between the cache table and the master table. An implementation has been developed that targets an FPGA-based network card in the environment of the China Financial Futures Exchange (CFFEX) which sustains 1- 10Gb/s bandwidth with latency of 400 to 700 nanoseconds, providing an 80- to 125-fold latency reduction compared to a fully optimized CPU-based solution, and a 2.2-fold reduction over an existing FPGA-based solution. |
Date of Acceptance: | 6-Mar-2017 |
URI: | http://hdl.handle.net/10044/1/45622 |
Publisher: | IEEE |
Copyright Statement: | © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. |
Sponsor/Funder: | Engineering & Physical Science Research Council (EPSRC) Engineering & Physical Science Research Council (E Engineering & Physical Science Research Council (E Commission of the European Communities |
Funder's Grant Number: | EP/P010040/1 516075101 (EP/N031768/1) PO 20131167 671653 |
Conference Name: | The 25th IEEE International Symposium on Field-Programmable Custom Computing Machines |
Keywords: | Science & Technology Technology Computer Science, Hardware & Architecture Engineering, Electrical & Electronic Computer Science Engineering FPGA finance algorithm low latency HPC |
Publication Status: | Accepted |
Start Date: | 2017-04-30 |
Finish Date: | 2017-05-02 |
Conference Place: | Napa, CA, USA |
Appears in Collections: | Computing Faculty of Engineering |