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Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework
| File | Description | Size | Format | |
|---|---|---|---|---|
 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems_28_3_2009.pdf | Accepted version | 346.97 kB | Adobe PDF | View/Open |
| Title: | Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework |
| Authors: | Liu, Q Constantinides, GA Masselos, K Cheung, PYK |
| Item Type: | Journal Article |
| Issue Date: | 1-Mar-2009 |
| URI: | http://hdl.handle.net/10044/1/15302 |
| DOI: | http://dx.doi.org/10.1109/TCAD.2009.2013541 |
| ISSN: | 0278-0070 |
| Publisher: | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
| Start Page: | 305 |
| End Page: | 315 |
| Journal / Book Title: | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS |
| Volume: | 28 |
| Issue: | 3 |
| Copyright Statement: | © 2009 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. |
| Publication Status: | Published |
| Appears in Collections: | Electrical and Electronic Engineering |