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High-resolution peripheral circuits for multi-state memristors and their related applications
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Wang-C-2024-PhD-Thesis.pdf | Thesis | 8.51 MB | Adobe PDF | View/Open |
Title: | High-resolution peripheral circuits for multi-state memristors and their related applications |
Authors: | Wang, Chaohan |
Item Type: | Thesis or dissertation |
Abstract: | The integration of memristors into CMOS technology holds immense potential and offers innovative possibilities for designing various systems in the beyond-CMOS era. A notable advantage of memristors is their ability to exhibit multi-state switching, allowing them to store multiple bits of information in a highly compact manner. However, certain challenges persist in the characterisation and design of multi-state memristive devices, circuits, and systems. This dissertation explores the latest advancements in memristor technologies of those with multi-state memristors and their integration with CMOS circuit design. By delving into the challenges, this thesis presents novel methodologies and solutions to memristor-related applications. The original contributions of this work are summarised in three aspects. Contribution 1: To exemplify the feasibility of employing multi-state memristors in memory design, in-house fabricated multi-state memristors are measured and the corresponding memristor model is used in the design to investigate the feasibility of using multi-state memristor in memory design. The RRAM employed in this design demonstrates successful read and write operations in simulation, enabling the storage and retrieval of 2-bit information. Contribution 2: To characterise memristors with a large number (up to 1 million devices on-chip) and switching resistance range, a novel high-resolution read-out circuit is designed with other collaborators to fulfil this requirement. Contribution 3: An innovative calibration scheme for analogue-to-digital converters that utilises memristors to optimise performance is invented. Within a feedback loop, the proposed scheme achieves this by dynamically adjusting the memristor's resistance. The designed calibration scheme effectively reduces the integral non-linearity and differential non-linearity, contributing to improved overall performance and accuracy. While the feasibility of these applications awaits full on-chip characterisation and verification due to the complex process of integrating memristors onto CMOS, the approach and simulated functionality offer an innovative path for designing circuits and applications with the assistance of memristors in forthcoming times. |
Content Version: | Open Access |
Issue Date: | Jan-2024 |
Date Awarded: | May-2024 |
URI: | http://hdl.handle.net/10044/1/111923 |
DOI: | https://doi.org/10.25560/111923 |
Copyright Statement: | Creative Commons Attribution NonCommercial NoDerivatives Licence |
Supervisor: | Papavassiliou, Christos |
Department: | Electrical and Electronic Engineering |
Publisher: | Imperial College London |
Qualification Level: | Doctoral |
Qualification Name: | Doctor of Philosophy (PhD) |
Appears in Collections: | Electrical and Electronic Engineering PhD theses |
This item is licensed under a Creative Commons License