Connect on the fly: enhancing and prototyping of cycle-reconfigurable modules
File(s)
Accepted version
Author(s)
Zhou, H
Niu, X
Yuan, J
Wang, L
Luk, W
Type
Conference Paper
Abstract
This paper introduces cycle-reconfigurable modules
that enhance FPGA architectures with efficient support for
dynamic data accesses: data accesses with accessed data size and
location known only at runtime. The proposed module adopts
new reconfiguration strategies based on
dynamic FIFOs
,
dynamic
caches
, and
dynamic shared memories
to significantly reduce
configuration generation and routing complexity. We develop
a prototype FPGA chip with the proposed cycle-reconfigurable
module in the SMIC 130-nm technology. The integrated module
takes less than the chip area of 39 CLBs, and reconfigures
thousands of runtime connections in 1.2 ns. Applications for large-
scale sorting, sparse matrix-vector multiplication, and Mem-
cached are developed. The proposed modules enable 1.4 and
11 times reductions in area-delay product compared with those
applications mapped to previous architectures and conventional
FPGAs.
that enhance FPGA architectures with efficient support for
dynamic data accesses: data accesses with accessed data size and
location known only at runtime. The proposed module adopts
new reconfiguration strategies based on
dynamic FIFOs
,
dynamic
caches
, and
dynamic shared memories
to significantly reduce
configuration generation and routing complexity. We develop
a prototype FPGA chip with the proposed cycle-reconfigurable
module in the SMIC 130-nm technology. The integrated module
takes less than the chip area of 39 CLBs, and reconfigures
thousands of runtime connections in 1.2 ns. Applications for large-
scale sorting, sparse matrix-vector multiplication, and Mem-
cached are developed. The proposed modules enable 1.4 and
11 times reductions in area-delay product compared with those
applications mapped to previous architectures and conventional
FPGAs.
Date Issued
2016-09-29
Date Acceptance
2016-06-15
Citation
2016
Publisher
IEEE
Copyright Statement
© 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Sponsor
Engineering & Physical Science Research Council (E
Commission of the European Communities
Engineering & Physical Science Research Council (E
Engineering & Physical Science Research Council (EPSRC)
Engineering & Physical Science Research Council (EPSRC)
Identifier
https://ieeexplore.ieee.org/document/7577332
Grant Number
20104124
671653
EP/K503733/1
EP/I012036/1
EP/K011715/1
Source
26th International Conference on Field-Programmable Logic and Applications
Subjects
Science & Technology
Technology
Computer Science, Software Engineering
Engineering, Electrical & Electronic
Computer Science
Engineering
Publication Status
Published
Start Date
2016-08-29
Finish Date
2016-09-02
Coverage Spatial
Lausanne, Switzerland
Date Publish Online
2016-09-29