A scalable FPGA-based architecture for depth estimation in SLAM
File(s)1902.04907v1.pdf (2.39 MB)
Accepted version
Author(s)
Boikos, K
Bouganis, C-S
Type
Conference Paper
Abstract
The current state of the art of Simultaneous Localisation and Mapping, or SLAM, on low power embedded systems is about sparse localisation and mapping with low resolution results in the name of efficiency. Meanwhile, research in this field has provided many advances for information rich processing and semantic understanding, combined with high computational requirements for real-time processing. This work provides a solution to bridging this gap, in the form of a scalable SLAM-specific architecture for depth estimation for direct semi-dense SLAM. Targeting an off-the-shelf FPGA-SoC this accelerator architecture achieves a rate of more than 60 mapped frames/sec at a resolution of 640×480 achieving performance on par to a highly-optimised parallel implementation on a high-end desktop CPU with an order of magnitude improved power consumption. Furthermore, the developed architecture is combined with our previous work for the task of tracking, to form the first complete accelerator for semi-dense SLAM on FPGAs, establishing the state of the art in the area of embedded low-power systems.
Date Issued
2019-03-29
Online Publication Date
2019-11-18T09:43:01Z
Date Acceptance
2019-01-20
ISBN
978-3-030-17226-8
Publisher
Springer
Start Page
181
End Page
196
Journal / Book Title
Applied Reconfigurable Computing
Volume
LNCS, 1444
Copyright Statement
© Springer Nature Switzerland AG 2019. The final authenticated version is available online at https://link.springer.com/chapter/10.1007/978-3-030-17227-5_14
Identifier
http://arxiv.org/abs/1902.04907v1
Source
ARC 2019
Subjects
cs.RO
cs.RO
cs.RO
cs.RO
Artificial Intelligence & Image Processing
Publication Status
Published
Start Date
2019-04-09
Finish Date
2019-04-11
Country
Darmstadt, Germany
Date Publish Online
2019-03-29