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  5. A micromachined zipping variable capacitor
 
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A micromachined zipping variable capacitor
File(s)
Pu-SH-2010-PhD-Thesis.pdf (6.66 MB)
Author(s)
Pu, Suan Hui
Type
Thesis
Abstract
Micro-electro-mechanical systems (MEMS) have become ubiquitous in recent years and
are found in a wide range of consumer products. At present, MEMS technology for
radio-frequency (RF) applications is maturing steadily, and significant improvements
have been demonstrated over solid-state components.
A wide range of RF MEMS varactors have been fabricated in the last fifteen years.
Despite demonstrating tuning ranges and quality factors that far surpass solid-state
varactors, certain challenges remain. Firstly, it is difficult to scale up capacitance
values while preserving a small device footprint. Secondly, many highly-tunable MEMS
varactors include complex designs or process flows.
In this dissertation, a new micromachined zipping variable capacitor suitable for
application at 0.1 to 5 GHz is reported. The varactor features a tapered cantilever that
zips incrementally onto a dielectric surface when actuated electrostatically by a pulldown
electrode. Shaping the cantilever using a width function allows stable actuation
and continuous capacitance tuning. Compared to existing MEMS varactors, this device
has a simple design that can be implemented using a straightforward process flow. In
addition, the zipping varactor is particularly suited for incorporating a highpermittivity
dielectric, allowing the capacitance values and tuning range to be scaled
up. This is important for portable consumer electronics where a small device footprint
is attractive.
Three different modelling approaches have been developed for zipping varactor
design. A repeatable fabrication process has also been developed for varactors with a
silicon dioxide dielectric. In proof-of-concept devices, the highest continuous tuning
range is 400% (24 to 121 fF) and the measured quality factors are 123 and 69 (0.1 and
0.7 pF capacitance, respectively) at 2 GHz. The varactors have a compact design and
fit within an area of 500 by 100 μm.
Date Issued
2010-04
Date Awarded
2010-05
URI
http://hdl.handle.net/10044/1/5608
DOI
https://doi.org/10.25560/5608
Copyright Statement
Attribution NoDerivatives 4.0 International Licence (CC BY-ND)
License URL
Attribution-NonCommercial-NoDerivatives 4.0 International
Advisor
Yeatman, Eric
Creator
Pu, Suan Hui
Publisher Department
Electrical and Electronic Engineering
Publisher Institution
Imperial College London
Qualification Level
Doctoral
Qualification Name
Doctor of Philosophy (PhD)
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