This work proposes a novel reconfigurable architecture for reducing the latency of JEDI-net, a Graph Neural
Network (GNN) based algorithm for jet tagging in particle
physics, which achieves state-of-the-art accuracy. Accelerating
JEDI-net is challenging since it requires low latency to deploy
the network for event selection at the CERN Large Hadron
Collider. This paper proposes an outer-product based matrix
multiplication approach customized for GNN-based JEDI-net,
which increases data spatial locality and reduces design latency.
It is further enhanced by code transformation with strength
reduction which exploits sparsity patterns and binary adjacency
matrices to increase hardware efficiency while reducing latency.
In addition, a customizable template for this architecture has
been designed and open-sourced, which enables the generation
of low-latency FPGA designs with efficient resource utilization
using high-level synthesis tools. Evaluation results show that our
FPGA implementation is up to 9.5 times faster and consumes up
to 6.5 times less power than a GPU implementation. Moreover,
the throughput of our FPGA design is sufficiently high to enable
deployment of JEDI-net in a sub-microsecond, real-time collider
trigger system, enabling it to benefit from improved accuracy.