A throughput-latency co-optimised cascade of convolutional neural network classifiers
File(s)
Accepted version
Author(s)
Kouris, Alexandros
Venieris, Stylianos
Bouganis, Christos-Savvas
Type
Conference Paper
Abstract
Convolutional Neural Networks constitute a promi-nent AI model for classification tasks, serving a broad span ofdiverse application domains. To enable their efficient deploymentin real-world tasks, the inherent redundancy of CNNs is fre-quently exploited to eliminate unnecessary computational costs.Driven by the fact that not all inputs require the same amount ofcomputation to drive a confident prediction, multi-precision cas-cade classifiers have been recently introduced. FPGAs comprise apromising platform for the deployment of such input-dependentcomputation models, due to their enhanced customisation ca-pabilities. Current literature, however, is limited to throughput-optimised cascade implementations, employing large batching atthe expense of a substantial latency aggravation prohibiting theirdeployment on real-time scenarios. In this work, we introduce anovel methodology for throughput-latency co-optimised cascadedCNN classification, deployed on a custom FPGA architecturetailored to the target application and deployment platform,with respect to a set of user-specified requirements on accuracyand performance. Our experiments indicate that the proposedapproach achieves comparable throughput gains with relatedstate-of-the-art works, under substantially reduced overhead inlatency, enabling its deployment on latency-sensitive applications.
Date Issued
2020-06-15
Date Acceptance
2019-11-12
Citation
2020, pp.1656-1661
Publisher
IEEE
Start Page
1656
End Page
1661
Copyright Statement
© 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Sponsor
Engineering & Physical Science Research Council (EPSRC)
Identifier
https://ieeexplore.ieee.org/document/9116248
Grant Number
EP/S030069/1
Source
Design, Automation and Test in Europe Conference (DATE 2020)
Publication Status
Published
Start Date
2020-03-09
Finish Date
2020-03-13
Coverage Spatial
Grenoble, France
Date Publish Online
2020-06-15