A 168 nW to 44.3 Mb/s adaptable TRNG with 400 mV attack-resilient hybrid RO core
File(s)
Accepted version
Author(s)
Özbek, Berkay
Constandinou, Timothy G
Type
Journal Article
Abstract
This letter presents an adaptable ring oscillator (RO)-true
random number generator (TRNG) that removes the fixed power–
throughput tradeoff by selecting delay-cell physics at run time. A hybrid
core uses a current-starved inverter in low-power (LP) mode to amplify
slew-limited jitter for high bit-efficiency at low frequency, and a latched
cross-coupled cell in high-performance (HP) mode to exploit regeneration time jitter over a wider band; both share a unified fast-by-slow sampling
path with XOR combining. Fabricated in 180 nm CMOS (265×490 µm),
the TRNG spans 0.8–2.0 V and −20 ◦C–80 ◦C, achieves 168 nW
(3.95 pJ/bit) in LP and 44.3 Mb/s in HP, and reaches near-ideal HP
entropy (0.999999999984). Long datasets pass NIST SP 800-22 (including
under 400 mV injection at the second harmonic), SP 800-90B, and AIS31.
A single, digitally-tunable IP thus delivers nanowatt standby entropy and
burst-mode throughput without architectural change.
random number generator (TRNG) that removes the fixed power–
throughput tradeoff by selecting delay-cell physics at run time. A hybrid
core uses a current-starved inverter in low-power (LP) mode to amplify
slew-limited jitter for high bit-efficiency at low frequency, and a latched
cross-coupled cell in high-performance (HP) mode to exploit regeneration time jitter over a wider band; both share a unified fast-by-slow sampling
path with XOR combining. Fabricated in 180 nm CMOS (265×490 µm),
the TRNG spans 0.8–2.0 V and −20 ◦C–80 ◦C, achieves 168 nW
(3.95 pJ/bit) in LP and 44.3 Mb/s in HP, and reaches near-ideal HP
entropy (0.999999999984). Long datasets pass NIST SP 800-22 (including
under 400 mV injection at the second harmonic), SP 800-90B, and AIS31.
A single, digitally-tunable IP thus delivers nanowatt standby entropy and
burst-mode throughput without architectural change.
Date Issued
2025-10-21
Date Acceptance
2025-10-10
Citation
IEEE Solid-State Circuits Letters, 2025, 8, pp.325-328
ISSN
2573-9603
Publisher
Institute of Electrical and Electronics Engineers
Start Page
325
End Page
328
Journal / Book Title
IEEE Solid-State Circuits Letters
Volume
8
Copyright Statement
Copyright © 2025 IEEE. This is the author’s accepted manuscript made available under a CC-BY licence in accordance with Imperial’s Research Publications Open Access policy (www.imperial.ac.uk/oa-policy)
License URL
Publication Status
Published
Date Publish Online
2025-10-14