Ultra-high frame rate and high resolution CMOS ISFET arrays for ion imaging
File(s)
Author(s)
Zeng, Junming
Type
Thesis
Abstract
For the past few decades, CMOS Ion Sensitive Field Effect Transistors (ISFETs) have been the main enabler in the field of biomedical imaging based on electrochemical sensors. The development of the ISFET has been following the same trend to a photo-diode in optical imagers, whose single device robustness has been well-established over the years. Mass-manufacturing ISFETs in CMOS has set a new trend for incorporating them into arrays to serve as a CMOS Lab-on-Chip (LoC) ion imaging front end, exploring high-resolution spatial-temporal bio-information.
As we continuously scale the size of the array while minimising the physical dimensions of each sensor, we also need to consider their readout architectures, to avoid significant compromises on their performances. From an array level, there exists a fundamental trade-off between the resolution of the array and its readout frame rate. In this thesis, we investigate novel system architectures to realise high resolution and high frame rate ISFET arrays on a minimum silicon area, with compensation techniques for CMOS ISFETs non-idealities considered.
To start off, we present a system utilising current mode signal processing techniques to minimise the sampling interval between two subsequent pixels, followed by 8 multiplexed current mode 10-bit ADCs for quantisation. The system is implemented in the AMS 0.35 μm CMOS process, operating at 3000 fps for an array size of 128×128, which is the fastest ISFET array reported in the literature. From this perspective, we promote the second generation LoC front-end consisting of a similar current mode readout topology while improving its performance both in mismatch and noise under the TSMC 0.18 μm process. Using row-parallel system architectures, we implement one 8-bit ADC per readout row to deliver a frame rate of 6100 fps with a same array size as before, further elevating the speed record for ISFET arrays.
Following this, we propose two innovative approaches focusing on array offset reduction and compensation in a per pixel basis. Each system features a pixel-level offset compensation circuit followed by 8-bit row-parallel ADCs as a part of a global feedback loop. Voltage and current mode architectures are implemented respectively while both can acquire ion interactions for up to 1000 fps with the same array size as before.
We conclude this work by applying the designed array for bio-analysis, in particular to discover the spatial-temporal origin of DNA amplifications, and to explore the impact of flow rates with a microfluidics setup, as well as to characterise the short-term dynamics of the ion-selective membranes. We demonstrate an end-to-end high speed and high resolution ion imaging platform that can be used to explore various biomedical-related information from a much wider spectrum.
As we continuously scale the size of the array while minimising the physical dimensions of each sensor, we also need to consider their readout architectures, to avoid significant compromises on their performances. From an array level, there exists a fundamental trade-off between the resolution of the array and its readout frame rate. In this thesis, we investigate novel system architectures to realise high resolution and high frame rate ISFET arrays on a minimum silicon area, with compensation techniques for CMOS ISFETs non-idealities considered.
To start off, we present a system utilising current mode signal processing techniques to minimise the sampling interval between two subsequent pixels, followed by 8 multiplexed current mode 10-bit ADCs for quantisation. The system is implemented in the AMS 0.35 μm CMOS process, operating at 3000 fps for an array size of 128×128, which is the fastest ISFET array reported in the literature. From this perspective, we promote the second generation LoC front-end consisting of a similar current mode readout topology while improving its performance both in mismatch and noise under the TSMC 0.18 μm process. Using row-parallel system architectures, we implement one 8-bit ADC per readout row to deliver a frame rate of 6100 fps with a same array size as before, further elevating the speed record for ISFET arrays.
Following this, we propose two innovative approaches focusing on array offset reduction and compensation in a per pixel basis. Each system features a pixel-level offset compensation circuit followed by 8-bit row-parallel ADCs as a part of a global feedback loop. Voltage and current mode architectures are implemented respectively while both can acquire ion interactions for up to 1000 fps with the same array size as before.
We conclude this work by applying the designed array for bio-analysis, in particular to discover the spatial-temporal origin of DNA amplifications, and to explore the impact of flow rates with a microfluidics setup, as well as to characterise the short-term dynamics of the ion-selective membranes. We demonstrate an end-to-end high speed and high resolution ion imaging platform that can be used to explore various biomedical-related information from a much wider spectrum.
Version
Open Access
Date Issued
2022-06
Date Awarded
2022-10
Copyright Statement
Creative Commons Attribution NonCommercial Licence
License URL
Advisor
Georgiou, Pantelakis
Publisher Department
Electrical and Electronic Engineering
Publisher Institution
Imperial College London
Qualification Level
Doctoral
Qualification Name
Doctor of Philosophy (PhD)