This thesis proposes optimisation methods for improving the timing performance
of digital circuits implemented in Field-Programmable Gate Arrays (FPGAs) with
the knowledge of process variation. With the current trend of transistor scaling,
improvements in fabrication processes alone will not completely solve the problem
of process variability due to the physical limitation of the process and materials.
Therefore, higher-level optimisation strategies, such as variation-aware and adaptive design are required to alleviate the erosion of overall timing performance. Three
novel optimisation methods, including variation-aware placement, routing and retiming are introduced in this thesis to reduce the impact of process variation on
FPGAs using measured variation maps.
By measuring and mapping real delay variation on FPGAs, traditional delay models
can be replaced with actual delay maps that allows variation-aware design methods
to be applied to produce more optimal designs on FPGAs. In this thesis, we propose
a new two-stage classification-based placement methodology to alleviate the impact
of delay variability while maintaining practical computational complexity and execution time. In addition, a variation-aware partial re-routing method is introduced
to improve the timing performance of designs by re-routing a portion of critical
and near-critical paths. Finally, a variation-aware retiming method is proposed to
further enhance timing performance after placement and routing.
Similar to the timing improvement achieved by full chipwise optimisation (19%), the
proposed two-stage placement, partial rerouting and retiming methods can provide
13% timing improvement. In addition, about 20 times speedup can be achieved
compared with full chipwise methods. Overall, the observed timing improvement
and reduction in execution time for MCNC benchmarks with the proposed optimisation methods clearly demonstrate their effectiveness and practicality against delay
variability in FPGAs.