This paper proposes optimizations of the methods and\r\nparameters used in both mathematical approximation and\r\nhardware design for logarithmic number system (LNS)\r\narithmetic. First, we introduce a general polynomial approximation\r\napproach with an adaptive divide-in-halves\r\nsegmentation method for evaluation of LNS arithmetic\r\nfunctions. Second, we develop a library generator that automatically\r\ngenerates optimized LNS arithmetic units with\r\na wide bit-width range from 21 to 64 bits, to support LNS\r\napplication development and design exploration. The basic\r\narithmetic units are tested on practical FPGA boards\r\nas well as software simulation. When compared with existing\r\nLNS designs, our generated units provide in most cases\r\n6% to 37% reduction in area and 20% to 50% reduction\r\nin latency. The key challenge for LNS remains on the application\r\nlevel. We show the performance of LNS versus\r\nfloating-point for realistic applications: digital sine/cosine\r\nwaveform generator, matrix multiplication and radiative\r\nMonte Carlo simulation. Our infrastructure for fast prototyping\r\nLNS FPGA applications allows us to efficiently\r\nstudy LNS number representation and its tradeoffs in speed\r\nand size when compared with floating-point designs.