In recent years, silicon nanowires (SiNW) have generated great interest for the fabrication
of nanometre-scale transistors, thermoelectric devices, solar cells, and biological/chemical
sensors. SiNWs, with minimum diameter ~10 nm, and lengths up to ~100 μm, may be
prepared by a variety of growth, etching and high-resolution lithographic techniques. In
particular, metal-assisted chemical etching (MACE) provides a low-cost method of
producing large arrays of high aspect ratio SiNWs.
This thesis investigates field-effect transistors (FETs) using SiNWs prepared by MACE.
Source/drain contacts to the FET are defined by titanium silicide. FETs using large-area
back-gates are found to be dominated by Schottky barriers (SB) at the source and drain.
The ISD-VSD and ISD-VBG characteristics are determined by thermionic emission across the
source SB, which may be lowered by the image-force potential, and by the local electric
field generated by the source/drain and gate potentials. These results demonstrate that
complete FET operation may be obtained by considering only the effect of SB lowering.
An inverted-channel SiNW FET is also presented, where the characteristics are determined
by both the contact SBs and the inversion layer in the NW. After subtracting the effect of
the SBs from the data, a long-channel MOSFET model is used to find the field-effect
electron mobility μFE ~100 cm2/Vs. FETs using parallel arrays of SiNWs are also
investigated. These devices show similar source/drain relationship to single SiNW devices,
but a weakened gate dependence, attributed to the aggregate response of multiple SiNWs
in parallel. Low-temperature measurements of these multi-wire devices from 300K to 20K
are used to extract the effective SB heights.