Hardware.jl — an MLIR-based Julia HLS flow (work in progress)
File(s)
Published version
Author(s)
Short, Benedict
McInerney, Ian
Wickerson, John
Type
Conference Paper
Abstract
Co-developing scientific algorithms and hardware accelerators requires domain-specific knowledge and large engineering resources. This leads to a slow development pace and high project complexity, which creates a barrier to entry that is too high for the majority of developers to overcome. We are developing a reusable end-to-end compiler toolchain for the Julia language entirely built on permissively-licensed open-source projects. This unifies accelerator and algorithm development by automatically synthesising Julia source code into high-performance Verilog.
Date Issued
2025-03-30
Date Acceptance
2025-03-07
Citation
2025
Copyright Statement
© 2025 Copyright held by the owner/author(s).
Source
5th Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE'25)
Publication Status
Published
Start Date
2025-03-30
Coverage Spatial
Rotterdam, Netherlands