Maximising parallel memory access for low latency FPGA designs
File(s)iscas22-submission-final.pdf (495.34 KB)
Accepted version
Author(s)
Denholm, Stewart
Luk, Wayne
Type
Conference Paper
Abstract
Memory-based computing stores pre-computed
function results in memory to be read at runtime. FPGAs group
together multiple block memories (BRAMs) to form this memory,
all accessed as a single monolithic device. We introduce a novel
ring-based architecture to leverage parallel accesses to these
constituent BRAMs, benefiting low latency applications that rely
on: highly-complex functions; numerical precision via iterative
computation; or many parallel data-paths accessing a shared
memory resource. The implemented function’s performance is
independent of its complexity, enabling significant latency reduc-
tions for compute-bound operations. We assess common functions
(sqrt, power, trigonometric, hyperbolic functions) on the Xilinx
Alveo U280 FPGA. Our function-agnostic memory-compute core
can serve 1024 parallel function calls at 300MHz and reduce
latency 4.4-29x versus traditional FPGA implementations.
function results in memory to be read at runtime. FPGAs group
together multiple block memories (BRAMs) to form this memory,
all accessed as a single monolithic device. We introduce a novel
ring-based architecture to leverage parallel accesses to these
constituent BRAMs, benefiting low latency applications that rely
on: highly-complex functions; numerical precision via iterative
computation; or many parallel data-paths accessing a shared
memory resource. The implemented function’s performance is
independent of its complexity, enabling significant latency reduc-
tions for compute-bound operations. We assess common functions
(sqrt, power, trigonometric, hyperbolic functions) on the Xilinx
Alveo U280 FPGA. Our function-agnostic memory-compute core
can serve 1024 parallel function calls at 300MHz and reduce
latency 4.4-29x versus traditional FPGA implementations.
Date Issued
2022-11-11
Date Acceptance
2022-01-14
Citation
2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2022, pp.1477-1481
Publisher
IEEE
Start Page
1477
End Page
1481
Journal / Book Title
2022 IEEE International Symposium on Circuits and Systems (ISCAS)
Copyright Statement
Copyright © 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Identifier
https://ieeexplore.ieee.org/document/9937955
Source
2022 IEEE International Symposium on Circuits and Systems (ISCAS)
Publication Status
Published
Start Date
2022-05-28
Finish Date
2022-06-01
Coverage Spatial
Austin, TX, USA
Date Publish Online
2022-11-11