Intracortical Brain-Machine Interfaces (iBMIs) have advanced significantly over the past
two decades, demonstrating their utility in various aspects, including neuroprosthetic control
and communication. To increase the information transfer rate and improve the devices’
robustness and longevity, iBMI technology aims to increase channel counts to access more
neural data while reducing invasiveness through miniaturisation and avoiding percutaneous
connectors (wired implants). However, as the number of channels increases, the raw data
bandwidth required for wireless transmission also increases becoming prohibitive, requiring
efficient on-implant processing to reduce the amount of data through data compression or
feature extraction.
The fundamental aim of this research is to develop methods for high-performance neural spike processing co-designed within low-power hardware that is scaleable for real-time
wireless BMI applications. The specific original contributions include the following:
Firstly, a new method has been developed for hardware-efficient spike detection, which
achieves state-of-the-art spike detection performance and significantly reduces the hardware
complexity. Secondly, a novel thresholding mechanism for spike detection has been introduced. By incorporating firing rate information as a key determinant in establishing the spike
detection threshold, we have improved the adaptiveness of spike detection. This eventually
allows the spike detection to overcome the signal degradation that arises due to scar tissue
growth around the recording site, thereby ensuring enduringly stable spike detection results.
The long-term decoding performance, as a consequence, has also been improved notably.
Thirdly, the relationship between spike detection performance and neural decoding accuracy has been investigated to be nonlinear, offering new opportunities for further reducing
transmission bandwidth by at least 30% with minor decoding performance degradation.
In summary, this thesis presents a journey toward designing ultra-hardware-efficient spike
detection algorithms and applying them to reduce the data bandwidth and improve neural
decoding performance. The software-hardware co-design approach is essential for the next
generation of wireless brain-machine interfaces with increased channel counts and a highly
constrained hardware budget.

The fundamental aim of this research is to develop methods for high-performance neural spike processing co-designed within low-power hardware that is scaleable for real-time wireless BMI applications. The specific original contributions include the following:

Firstly, a new method has been developed for hardware-efficient spike detection, which achieves state-of-the-art spike detection performance and significantly reduces the hardware complexity. Secondly, a novel thresholding mechanism for spike detection has been introduced. By incorporating firing rate information as a key determinant in establishing the spike detection threshold, we have improved the adaptiveness of spike detection. This eventually allows the spike detection to overcome the signal degradation that arises due to scar tissue growth around the recording site, thereby ensuring enduringly stable spike detection results. The long-term decoding performance, as a consequence, has also been improved notably. Thirdly, the relationship between spike detection performance and neural decoding accuracy has been investigated to be nonlinear, offering new opportunities for further reducing transmission bandwidth by at least 30\% with only minor decoding performance degradation.

In summary, this thesis presents a journey toward designing ultra-hardware-efficient spike detection algorithms and applying them to reduce the data bandwidth and improve neural decoding performance. The software-hardware co-design approach is essential for the next generation of wireless brain-machine interfaces with increased channel counts and a highly constrained hardware budget.