Dynamic C-slow pipelining for HLS
File(s)
Accepted version
Author(s)
Cheng, Jianyi
Wickerson, John
Constantinides, George
Type
Conference Paper
Abstract
In high-level synthesis (HLS), loop pipelining allows
multiple iterations of a loop to be executed concurrently. The
start time of the operations in each iteration can be determined
either at compile time (static pipelining) or at run time (dynamic
pipelining). There has been recent interest in dynamic pipelining,
as it can overcome the conservatism of static analysis, potentially
achieving better performance.
In order to ensure correctness in the presence of memory
dependences, existing state-of-the-art dynamic pipelining algo-
rithms schedule control flow between basic blocks in the original
program order even if they allow pipelining of data flow. This
allows source code to be compiled compositionally, ‘stitching
together’ the resulting hardware components to produce the
final hardware design. However, this approach can result in
suboptimal throughput.
In this paper we propose a technique to statically determine
a set of possible memory-legal control flows for nested loops,
together with a scheduler component able to select from that
set efficiently at run time, enabling dynamic execution of control
as a C-slow pipeline. An empirical evaluation on a range of
applications suggests that by using this approach, we can obtain
2.9× speedup with 7% area overhead compared to a dynamic
scheduling approach with sequential control flow
multiple iterations of a loop to be executed concurrently. The
start time of the operations in each iteration can be determined
either at compile time (static pipelining) or at run time (dynamic
pipelining). There has been recent interest in dynamic pipelining,
as it can overcome the conservatism of static analysis, potentially
achieving better performance.
In order to ensure correctness in the presence of memory
dependences, existing state-of-the-art dynamic pipelining algo-
rithms schedule control flow between basic blocks in the original
program order even if they allow pipelining of data flow. This
allows source code to be compiled compositionally, ‘stitching
together’ the resulting hardware components to produce the
final hardware design. However, this approach can result in
suboptimal throughput.
In this paper we propose a technique to statically determine
a set of possible memory-legal control flows for nested loops,
together with a scheduler component able to select from that
set efficiently at run time, enabling dynamic execution of control
as a C-slow pipeline. An empirical evaluation on a range of
applications suggests that by using this approach, we can obtain
2.9× speedup with 7% area overhead compared to a dynamic
scheduling approach with sequential control flow
Date Issued
2022-06-03
Date Acceptance
2022-03-21
Citation
2022, pp.1-10
Publisher
IEEE
Start Page
1
End Page
10
Copyright Statement
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Identifier
https://ieeexplore.ieee.org/document/9786096
Source
IEEE International Symposium on Field-Programmable Custom Computing Machines
Publication Status
Published
Start Date
2022-05-15
Finish Date
2022-05-18
Coverage Spatial
New York City, NY, USA
Date Publish Online
2022-06-03