We investigate the influence of Schottky barrier lowering in Si nanowire field-effect transistors,
using nanowires prepared by metal-assisted chemical etching. The experimental electrical characteristics of a p-channel transistor are modeled using thermionic emission of holes across the reverse-biased source Schottky barrier. This barrier is lowered by the image-force potential, and by the electric field generated by both source-drain and gate voltages. The gate voltage lowers the barrier height directly and in addition, modulates the effect of the source-drain voltage on barrier
lowering.