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  5. RSQP: problem-specific architectural customization for accelerated convex quadratic optimization
 
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RSQP: problem-specific architectural customization for accelerated convex quadratic optimization
File(s)
ISCA_RSQP_CameraReady.pdf (1.19 MB)
Accepted version
Author(s)
Wang, Maolin
McInerney, Ian
Stellato, Bartolomeo
Boyd, Stephen
Kwok-Hay So, Hayden
Type
Conference Paper
Abstract
Convex optimization is at the heart of many performance-critical applications across a wide range of domains. Although many high-performance hardware accelerators have been developed for specific optimization problems in the past, designing such accelerator is a challenging task and the resulting computing architecture is often so specific to the targeted application that they can hardly be reused even in a related application within the same domain. To accelerate general-purpose optimization solvers that must operate on diverse user input during run time, an ideal hardware solver should be able to adapt to the provided optimization problem dynamically while achieving high performance and power-efficiency. In this work, a hardware-accelerated general-purpose quadratic program solver, called RSQP, with reconfigurable functional units and data path that facilitate problem-specific customization is presented. RSQP uses a string-based encoding to describe the problem structure with fine granularity. Based on this encoding, functional units and datapath customized to the sparsity pattern of the problem are created by solving a dictionary-based lossless string compression problem and a mixed integer linear program respectively. RSQP has been integrated to accelerate the general-purpose quadratic programming solver OSQP and has been tested using an extensive benchmark with 120 optimization problems from 6 application domains. Through architectural customization, RSQP achieves up to 7× performance improvement over its baseline generic design. Furthermore, when compared with a CPU and a GPU-accelerated implementation, RSQP achieves up to 31.2× and 6.9× end-to-end speedup on these benchmark programs, respectively. Finally, the FPGA accelerator operates at up to 6.6× lower dynamic power consumption and up to 22.7× higher power efficiency over the GPU implementation, making it an attractive solution for power-conscious datacenter applications.
Date Issued
2023-06
Date Acceptance
2023-04-07
Citation
Proceedings of the 50th Annual International Symposium on Computer Architecture (ISCA '23), 2023, 73, pp.1-12
URI
http://hdl.handle.net/10044/1/103947
URL
https://dl.acm.org/doi/10.1145/3579371.3589108
DOI
https://www.dx.doi.org/10.1145/3579371.3589108
ISBN
979-8-4007-0095-8
Publisher
Association for Computing Machinery
Start Page
1
End Page
12
Journal / Book Title
Proceedings of the 50th Annual International Symposium on Computer Architecture (ISCA '23)
Volume
73
Copyright Statement
© Author(s) 2023. This is the author's version of the work. It is posted here for
your personal use. Not for redistribution. The definitive version was published
in ISCA '23: Proceedings of the 50th Annual International Symposium on Computer Architecture, https://doi.org/10.1145/3579371.3589108
Identifier
https://dl.acm.org/doi/10.1145/3579371.3589108
Source
ISCA '23: The 50th Annual International Symposium on Computer Architecture
Publication Status
Published
Start Date
2023-06-17
Finish Date
2023-06-21
Coverage Spatial
Orlando, FL, USA
Date Publish Online
2023-06-17
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