Accelerating large-scale graph processing with FPGAs: lesson learned and future directions
File(s)
Published version
Author(s)
Type
Conference Paper
Abstract
Processing graphs on a large scale presents a range of difficulties, including irregular memory access patterns, device memory limitations, and the need for effective partitioning in distributed systems, all of which can lead to performance problems on traditional architectures such as CPUs and GPUs. To address these challenges, recent research emphasizes the use of Field-Programmable Gate Arrays (FPGAs) within distributed frameworks, harnessing the power of FPGAs in a distributed environment for accelerated graph processing. This paper examines the effectiveness of a multi-FPGA distributed architecture in combination with a partitioning system to improve data locality and reduce inter-partition communication. Utilizing Hadoop at a higher level, the framework maps the graph to the hardware, efficiently distributing pre-processed data to FPGAs. The FPGA processing engine, integrated into a cluster framework, optimizes data transfers, using offline partitioning for large-scale graph distribution. A first evaluation of the framework is based on the popular PageRank algorithm, which assigns a value to each node in a graph based on its importance. In the realm of large-scale graphs, the single FPGA solution outperformed the GPU solution that were restricted by memory capacity and surpassing CPU speedup by 26x compared to 12x. Moreover, when a single FPGA device was limited due to the size of the graph, our performance model showed that a distributed system with multiple FPGAs could increase performance by around 12x. This highlights the effectiveness of our solution for handling large datasets that surpass on-chip memory restrictions.
Date Issued
2024-03-01
Date Acceptance
2023-12-23
Citation
Open Access Series in Informatics, 2024, 116, pp.6:1-6:12
ISSN
2190-6807
Publisher
Schloss Dagstuhl
Start Page
6:1
End Page
6:12
Journal / Book Title
Open Access Series in Informatics
Volume
116
Copyright Statement
© Marco Procaccini, Amin Sahebi, Marco Barbone, Wayne Luk, Georgi Gaydadjiev, and Roberto Giorgi;
licensed under Creative Commons License CC-BY 4.0 (https://creativecommons.org/licenses/by/4.0/)
licensed under Creative Commons License CC-BY 4.0 (https://creativecommons.org/licenses/by/4.0/)
License URL
Source
15th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 13th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2024)
Publication Status
Published
Start Date
2024-01-18
Coverage Spatial
Munich, Germany